Summary
What you’ll impact
The Applications Engineer will act as the primary technical liaison for customers integrating the organization's silicon IP, guiding them through verification, physical implementation, and sign‑off. The role involves debugging integration issues, developing reference flows, delivering training, and collaborating with internal teams to improve IP deliverables. This customer‑facing position requires strong ASIC/SoC expertise and the ability to translate complex technical findings into actionable guidance.
Responsibilities
What you'll do
- Help customers successfully evaluate, integrate, verify, and physically implement our silicon IP in their SoCs.
- Be the technical bridge between customers and our design, verification, physical design, and characterization teams—helping customers stand up verification environments, close coverage and timing, resolve integration issues, and keep tapeouts on schedule.
- Serve as the primary technical point of contact for customers integrating our silicon IP, from RTL simulation and UVM testbench setup through synthesis, floorplanning, place-and-route, timing closure, and signoff.
- Debug customer-reported issues across the RTL, testbench, constraints, and physical implementation boundary; distinguish IP defects and deliverable issues from configuration errors, protocol misunderstandings, constraints, or implementation choices.
- Develop and maintain reference verification environments, example testbenches, implementation flows, floorplan guidance, and integration collateral—including SDC and UPF templates—that reduce customer ramp time.
- Deliver onsite and remote technical training on IP architecture, verification methodology, verification IP usage, coverage closure, timing models, physical abstracts, and implementation best practices.
- Partner with engineering and product leaders to aggregate field evidence, prioritize corrective work, and shape future capabilities, deliverables, and release content.
- Support pre-sales technical evaluations by helping prospective customers assess IP quality, verification collateral, PPA, floorplan compatibility, node/process readiness, and integration effort.
- Lead architecture-to-signoff reviews of customer integrations, identify implementation risks, and recommend corrective actions across configuration, verification, performance, timing, power, and area.
- Exercise upcoming IP releases and customer collateral in representative integration flows; document gaps and work with engineering owners to close them before external delivery.
- Advise customers on interface and protocol integration, multi-voltage and power-domain design, DFT stitching at the IP boundary, and node-specific signoff requirements.
- Turn recurring support cases into reusable enablement—including reference examples, diagnostic playbooks, automation, and self-service guidance—that shortens resolution time for customers and the field team.
- Track and report field issues and recurring integration patterns to inform the IP roadmap, deliverable quality, and process-node support priorities.
Requirements
What you’ll bring
- BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- 5+ years of experience in ASIC/SoC verification, physical design, silicon IP integration, or a closely related applications engineering role.
- Strong scripting and automation skills—Python, TCL, Make, or shell—for building flows, regressions, and debug tooling.
- Hands-on experience integrating third-party or internally licensed silicon IP, such as soft or hard macros, protocol or interface IP, interconnect, standard-cell libraries, or memory compilers.
- Experience diagnosing complex integration issues and translating deep technical findings into clear, actionable guidance for customers and internal teams.
- Familiarity with multiple foundries or process nodes and the verification, PPA, reliability, and signoff challenges associated with them.
- One or more of the following experience areas: Strong SystemVerilog/UVM skills, comfort reading and debugging RTL, and experience with coverage-driven verification using simulators such as Xcelium, VCS, or Questa.
- Practical experience with synthesis, floorplanning, place-and-route, and static timing analysis using tools such as Cadence Innovus, Synopsys ICC2/Fusion Compiler, PrimeTime, or Tempus.
- Working knowledge of timing models and physical abstracts (Liberty/ECSM/CCS and LEF), constraints and low-power intent (SDC and UPF), and signoff flows (STA, IR/EM, DRC/LVS).
- Willingness to travel to customer sites approximately 20–30%, depending on business needs.